In high speed personal computers, system performance may be limited in part by the execution time of CPU write cycles. This is especially apparent in systems employing error correcting code (ECC) memories. Overall system performance is affected to a large degree by the performance of its memory subsystem. A memory subsystem comprises two major elements, a memory controller and a main memory. A microprocessor or CPU, initiates bus cycles to the memory controller. These bus cycles can include both data read and data write requests. For CPU read cycles, the CPU must wait for data to return from the main memory before continuing execution. For write cycles, the CPU must wait for the memory system to complete writing data into memory.
Performance is limited in part by the time delay inherent in reading data from and writing data to the memory. This limitation becomes readily apparent with modern processors running at 50 Mhz and above. Some modern processors use integrated store-through caches in order to optimize performance. These caches can provide read data to the processing core of the microprocessor in an expeditious manner for read cycles. When this is done, write cycle performance tends to dominate and limit the overall system performance.
One prior art performance enhancement employed by some systems is a write buffer. A write buffer is a block of logic positioned between the processor and the memory system. The write buffer is capable of storing one or more complete processor write cycles. Processor write cycles include address, data, and control information. Write buffers operate by first capturing the cycle information in buffers and then signalling the microprocessor that the write cycle is complete. The write buffer then acts to complete the cycle to the remainder of the system. Write buffers enhance performance by signalling the microprocessor that the write cycle is complete sooner than would normally be possible. The write buffer then appears to the remainder of the system like the processor itself, and waits for the buffered cycle to complete. In the meantime, the microprocessor is free to complete further internal operations, which are possibly assisted by the internal cache as previously discussed.
Write buffers can include the capability to buffer more than one write cycle at any given time and thereby improve system performance in cases in which the microprocessor requires that several write cycles be completed before continuing to the next read operation. Write buffers, however, can only provide limited improvement to processor performance. Read cycles to main memory must be delayed until any write buffer contents are completely stored into main memory. Sequential write cycles, beyond the depth of any given write buffer, must also wait to complete until space becomes available in the write buffer. Consequently, systems employing write buffers may still be limited by the performance of write cycles.
Currently, error correcting code (ECC) memory subsystems are being introduced into personal computer systems. These memory subsystems use an error correcting code word that is stored along with required processor data. ECC memory subsystems improve system reliability by detecting and correcting single bit memory errors. The ECC code word is calculated on the basis of a selected atomic unit of data. In PS/2 personal computer systems, this code word is calculated on the basis of a 32-bit wide data word, and requires 7-bits for code storage. However, most personal computer software is written to operate on 8-bit or 16-bit processors. Consequently, even though many new systems employ 32-bit processors, a large number of read and write cycles occur as 8 or 16 bit operations. These cycles are referred to here as "partial write cycles", in that the size of the write data is less than the size (32 bits) of the minimum ECC memory atomic data unit. When the microprocessor executes a write of less than an atomic memory unit, the memory subsystem must execute a special read-modify-write (RMW) or partial write cycle.
During a RMW cycle, the CPU transmits bus definition signals along with the data to be written and the address where the data is to be written. Such bus definition signals indicate a write cycle for data having less than 32 bits. Thirty two bits of data along with ECC correction code are then read from the main memory at such address. The data (8, 16, or 24 bits) to be written is merged with old data read from the addressed location to form a new 32-bit word. A new 32 bit word correction code is calculated and the resultant new 32 bit word with code is written into main memory.
Such complex cycle is required in order to maintain relevant correction code storage information at each atomic memory address. In an ECC memory system, the wait time for write cycles becomes more pronounced when a partial write cycle occurs and the memory controller must execute both a main memory read and a main memory write for a single processor operation.
In summary, system performance in high speed personal computers is limited in large part by the speed at which write cycles occur into main memory. This limitation is more pronounced in systems employing ECC memory, whenever a large percentage of partial writes occur, since these partial write cycles are relatively lengthy cycles.